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351	Cache and I/O Efficient Functional Algorithms Guy E. Blelloch Robert Harper Carnegie Mellon University Add to Reading List Source URL: www.cs.cmu.edu Language: English - Date: 2012-10-30 13:00:38 Computer hardware Analysis of algorithms Sorting algorithms Memory management Models of computation Cache-oblivious algorithm CPU cache Merge sort Compiler optimization Cache Computer memory Computing
352	The Cache Performance of Blocked Monica S. Lam, Add to Reading List Source URL: suif.stanford.edu Language: English - Date: 2003-10-16 22:29:20 Computer hardware Compiler optimizations CPU cache Central processing unit Data Memory hierarchy Cache-oblivious algorithm Loop tiling Cache Computer memory Computing
353	White Paper Exploring the ARM® Cortex®-M7 Core: Providing Adaptability for the Add to Reading List Source URL: cache.freescale.com Language: English - Date: 2015-02-25 17:24:03 Electronics Freescale Semiconductor Multi-core processor ARM Cortex-M Microcontroller Joint Test Action Group CPU cache Tegra Advanced Microcontroller Bus Architecture Computer architecture Computer hardware ARM architecture
354	Lecture 10: Memory Hierarchy—3 Cs and 7 Ways to Reduce Misses Professor David A. Patterson Computer Science 252 Spring 1998 Add to Reading List Source URL: www.cs.berkeley.edu Language: English - Date: 1998-02-26 13:05:55 Computing Cache CPU cache Alpha 21164 Dynamic random-access memory Memory hierarchy Computer architecture Computer memory Computer hardware Central processing unit
355	Probabilistic Instruction Cache Analysis using Bayesian Networks Mark Bartlett, Iain Bate, James Cussens and Dimitar Kazakov Department of Computer Science University of York York, UK Add to Reading List Source URL: www.cs.york.ac.uk Language: English - Date: 2012-05-02 15:17:12 Cache CPU cache Central processing unit Computer memory Bayesian network Graphical model Bayesian inference Worst-case execution time Acumem SlowSpotter Statistics Bayesian statistics Statistical models
356	Lecture 18: Multiprocessors 2: Snooping v. Directory Coherency, Memory Consistency Models Professor David A. Patterson Computer Science 252 Add to Reading List Source URL: www.cs.berkeley.edu Language: English - Date: 1998-04-10 13:28:22 MESI protocol CPU cache Cache Central processing unit Write-once Cache coherency Computer hardware Computing
357	On Memory-Bound Functions for Fighting Spam Cynthia Dwork1 , Andrew Goldberg1, and Moni Naor2? 1 Microsoft Research, SVC 1065 L’Avenida Add to Reading List Source URL: www.hashcash.org Language: English - Date: 2005-01-15 19:23:52 Computer memory Statistics CPU cache Central processing unit Lookup table Bit array Random walk Logarithm Cache-oblivious algorithm Computing Arrays Cache
358	Second Workshop on Hot Topics in Autonomic Computing. June 15, 2007. Jacksonville, FL. Categorizing and differencing system behaviours Raja R. Sambasivan, Alice X. Zheng, Eno Thereska, Gregory R. Ganger Carnegie Mellon U Add to Reading List Source URL: www.pdl.cmu.edu Language: English - Date: 2007-05-16 09:09:00 Data analysis Data mining Geostatistics Machine learning Computer cluster K-means clustering CPU cache Distributed computing Statistics Computing Cluster analysis
359	FP 14.1 Intelligent RAM (IRAM): Chips that remember and compute David Patterson, Thomas Anderson, Neal Cardwell, Richard Fromm, Kimberley Keeton, Christoforos Kozyrakis, Randi Thomas, and Kathy Yelick Computer Science/EE Add to Reading List Source URL: iram.cs.berkeley.edu Language: English - Date: 1997-02-12 03:04:51 CPU cache Alpha 21164 Dynamic random-access memory The Berkeley IRAM Project PA-8000 Computer memory Computer hardware Computing
360	Instruction Cache Prediction Using Bayesian Networks Mark Bartlett and Iain Bate and James Cussens1 Abstract. Storing instructions in caches has led to dramatic increases in the speed at which programs can execute. Howev Add to Reading List Source URL: www.cs.york.ac.uk Language: English - Date: 2012-05-02 15:17:20 Computer memory Bayesian network Information Electronics Electronic engineering Cache pollution Classic RISC pipeline Cache CPU cache Central processing unit

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